Mixed Signal Design Verification (MSDV) Engineer

Mixed Signal Design Verification EngineerPosition SummaryIntegrated Circuit Solutions (ICS) Group is seeking a highly motivated Mixed Signal Design Verification Engineer with a strong background in analog and mixed-signal IC design verification. In this role, you will be responsible for pre-tapeout verification of silicon design, ensuring the part will meet all stated specifications and behavior and is manufacturable and testable. Familiarity with power converters and the challenges of power design is a plus.

This position requires strong communication skills and leadership qualities. The selected individual will assume a technical contributor role with the ability to identify and implement opportunities for continuous improvement and work collaboratively with a diverse team of analog and digital designers, layout engineers, and system architects to ensure first-pass silicon success and high-quality product delivery.Key ResponsibilitiesOperate as DV lead to drive quality product tapeoutsDevelop a detailed pre-Si verification plan, create simulation environments, and mixed-signal behavioral models and work closely with design and systems teams to execute automated regressions to ensure coverage goals are metInterface across different functional groups such as systems, applications, test, silicon validation, etc. to ensure product design was verified correctly and completely and that end-product fits customer’s needsBuild relationships with internal teams by closely interacting with them to identify and solve design related problemsAnalyze simulation results, identify root causes of failures, and provide actionable recommendations.Participate in design reviews, verification reviews, and silicon bring-up activities.Support post-silicon validation and correlation between simulation and measured silicon performance.Required QualificationsStrong familiarity with EDA design tools such as Cadance Virtuoso design environmentStrong familiarity with analog, digital and mixed-signal design and tool flowExtensive experience with Verilog/Verilog-A/SystemVerilog and Universal Verification Methodology (UVM) to run automated regressionsWorking knowledge of Unix shell, TCL, Perl, Python and SKILL scripting languagesExcellent analytical, troubleshooting, and communication skills.Bachelor’s, Master’s or PhD degrees in Electrical Engineering or related field of studyPreferred QualificationsExperience developing verification environment for integrated circuits that incorporate I2C, PMBus or SPI type communication protocolsUnderstand power management chip architectures (ideal diodes, e-fuses, switching converters etc)Experience with lab validation is a plusUnderstand ESD, reliability, and electro-migration verificationExperience with semiconductor manufacturing processes and design-for-test methodologies.Familiarity with version control systems such as DesignSync, SVN, Git.Success FactorsThe ideal candidate is detail-oriented, analytical, and collaborative, with a passion for delivering robust analog and mixed-signal designs.

They thrive in a fast-paced development environment, communicate effectively across cross-functional teams, and are committed to continuous improvement of verification methodologies.BenefitsCompetitive salary and performance-based incentivesComprehensive health, dental, and vision insuranceRetirement savings plan with company matchPaid time off and company holidaysProfessional development and training opportunitiesCollaborative and innovative engineering environmentOpportunities to work on cutting-edge semiconductor technologiesAbout the teamJoin a global team at the forefront of innovation and play a key role in shaping the future of Nexperia’s product offerings.Nexperia is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, color, creed, religion, national origin, ancestry, citizenship status, age, sex or gender (including pregnancy, childbirth and pregnancy-related conditions), gender identity or expression (including transgender status), sexual orientation, marital status, military service and veteran status, physical or mental disability, genetic information, or any other characteristic protected by applicable federal, state or local laws and ordinances. Nexperia’s management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, TeamNexperian’s activities, access to facilities and programs and general treatment during employment.More information?For more details please contact: acquisition based on Nexperia vacancies is not appreciated. Nexperia job adverts are Nexperia copyright material and the word Nexperia is a registered trademark.D&I StatementAs an equal-opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better.

We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.In addition, we offer our colleagues the possibility to join employee resource groups such as the Pride Network Group or global and local Women's groups. Nexperia is committed to increasing women in management positions to 30% by 2030.SummaryLocation: DallasType: Full time