Mid-Senior ASIC RTL Verification Engineer (DDR/Memory IP)

A technology company in Santa Clara is seeking an adaptive Design Verification Engineer to improve ASIC design verification processes. The ideal candidate has over 10 years of experience and expertise in C/C++, Verilog, and modern verification libraries. Responsibilities include developing tests for functional verification and collaborating with cross-functional teams. This position is contract-based and encourages a supportive workplace.
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