Memory Test FPGA Engineering Manager - Lead & Deliver

Teradyne is seeking an experienced FPGA Engineering Manager to lead a team developing cutting-edge memory test solutions. You will oversee RTL/FPGA design, coordinate with hardware/software/firmware groups, and ensure timely delivery of high-quality products.

The role requires a strong background in Digital ASIC/FPGA design, leadership of 4–6 engineers, and hands-on participation in RTL coding and lab validation. Competitive salary and discretionary bonuses accompany challenging projects.