Apple Inc. in Cupertino, California, is seeking a Senior IC Design Engineer to lead power reduction and physical design for advanced node SoCs.
You will perform static and dynamic power analysis, implement low power techniques, fix violations, and drive tape-out readiness with partitioning, floorplanning, and ECOs. You will develop CAD tool flows, script in TCL/Perl/Python, collaborate with logic design, and push design closure through sign-off for timing, PDV, and reliability.
#J-18808-LjbffrLow-Power Physical Design Engineer (7nm+) in cupertino at Unknown Company
This position is listed as full time and onsite.