Meta Reality Labs in Sunnyvale, CA seeks a Design Verification Engineer for ML accelerators. You will work with researchers and engineers to implement testing infrastructure validating core IPs and contributing to ML algorithm development and optimization.
Collaboration with design, model, emulation, and silicon validation teams is essential. Ideal candidates have 10+ years of SystemVerilog/UVM verification experience, IP/SoC verification exposure, and strong scripting with Python and TCL.
#J-18808-LjbffrLead Verification Engineer - ML Accelerator IP in sunnyvale at Unknown Company
This position is listed as full time and onsite.