Lead TileLink & Interconnect Architect (Chisel)

SiFive, Inc. is seeking a principal-level hardware engineer to design industry-leading CPU and interconnect IP. This role involves working on customizable IP and enhances the RISC-V architecture for SOC designs across various applications.

The ideal candidate should have strong RTL design skills and a solid educational background. The position offers a competitive salary range and numerous benefits, including healthcare, paid time off, and more.