Responsibilities
- Drive hands‑on development and validation of Pegasus DRC and LVS runsets for advanced semiconductor nodes.
- Design, enhance, and maintain automation frameworks for regression execution, issue detection, and validation reporting.
- Collaborate closely with R&D and cross‑functional teams to debug issues, validate fixes, and improve solution quality and performance.
- Provide technical enablement and support to customers on tool usage and advanced physical verification methodologies.
- Apply and help refine best practices for runset development, validation, and quality assurance.
- Work independently on complex technical deliverables while contributing knowledge and guidance within the team.
- Partner with internal teams to support predictable and timely delivery of physical verification solutions.
Requirements
- MS degree with 5+ years of experience or PhD with 3+ years in Electrical Engineering, Computer Science, or related field.
- Strong understanding of semiconductor design flows and physical verification methodologies.
- Proven hands‑on experience developing and validating DRC and LVS runsets using Pegasus or comparable tools such as Calibre, ICV, or Assura.
- Experience building or maintaining automation for regression, validation, and reporting.
- Proficiency in TCL, Python, and/or Perl, with experience in Linux/Unix environments.
- Solid understanding of advanced process technologies and verification methodologies (e.g., ground rules, fill, ESD).
- Familiarity with chip fabrication processes and advanced‑node challenges, including multi‑die designs.
- Nice-to-have: Experience with PERC and Fill runsets.
Certifications & Qualifications
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