Cadence Design Systems in California is seeking a Lead Software Engineer - Low Power Verification to advance UPF debug features and RTL support as part of Palladium and Protium flows.
You will enhance UPF performance, scale event logging for multi-billion-gate designs, and help document end-to-end workflows with SystemVerilog and UPF examples. Collaboration across R&D, PE and AE teams is required, with a focus on high-quality, scalable software.
#J-18808-LjbffrLead Software Engineer - Low-Power Verification (UPF) in san jose at Unknown Company
This position is listed as full time and onsite.