Cadence Design Systems in San Jose is seeking a Lead Software Engineer to advance low-power verification software for Palladium and Protium platforms. You will improve UPF compilation performance, add support for new IEEE 1801 LRM revisions, and document end-to-end workflows with SystemVerilog and UPF examples.
You will work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, Dielets) and ensure code and docs stay in sync through example-driven checks.
#J-18808-LjbffrLead Software Engineer: Low-Power Verification (Equity) in san jose at Unknown Company
This position is listed as full time and onsite.