Astera Labs in San Jose, CA seeks a Principal Design Verification Engineer to lead functional verification of advanced SoCs for server and networking applications. You will drive test planning, development, and coverage closure across the full verification lifecycle.
You should have 8+ years of SoC verification experience, strong SystemVerilog/UVM expertise, and hands-on scripting with Python or C/C++. The role offers a competitive salary and potential discretionary bonuses.
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This position is listed as full time and onsite.