Lead SOC Design Engineer – Timing Closure & RTL

Jobtailor is seeking an experienced SOC design lead to guide timing closure for Palladium and Protium tapeouts. The role involves leading a team on SOC/sub-system implementations, RTL synthesis, floor planning, clock-tree building, and full physical verification.

Candidates should have a BS in Electrical Engineering with substantial experience, proficiency with Cadence tools, experience at advanced nodes (5nm/3nm/2nm) and Linux scripting, and the ability to coordinate FE RTL with BE verification