Lead SoC Design Engineer – RTL, Synthesis & Tape-out

Cadence in San Jose is hiring for a critical role leading teams to implement SOCs and subsystem chips. This position demands extensive experience in RTL synthesis and advanced technology processes. Ideal candidates should have a strong engineering background, proficiency with Cadence tools, and experience in collaborating with cross-functional teams.

The role offers a competitive salary range from $136,500 to $253,500 based on qualifications, along with robust benefits including 401(k), stock purchase plans, and generous vacation policies.