Lead SoC Design Engineer – RTL, Synthesis & Tape-out

Cadence in Cary, North Carolina, is looking for an experienced engineer to lead implementations of SOCs or subsystem chips. The ideal candidate will have a strong background in RTL synthesis and optimizations, as well as experience with advanced technologies.

Responsibilities include leading team efforts, working on physical verification, and interfacing with design teams. A competitive salary range of $136,500 to $253,500 applies, along with comprehensive benefits.