Lead RTL/SoC Design Engineer

TetraMem INC in Fremont is seeking a Lead RTL Designer to spearhead design, simulation, and verification for our innovative ASIC/SoC products. The role demands a deep understanding of digital design methodologies and the ability to mentor junior engineers.

Ideal candidates will possess a master's or PhD with at least 5 years of experience, along with proficiency in Verilog and System Verilog. We offer a competitive compensation package and excellent benefits.