Celero Communications, Inc. is seeking a Principal Design Validation & Test (DVT) Engineer in Irvine, CA to spearhead post-silicon validation for next-generation coherent DSP ASICs enabling AI and hyperscale networking.
You will drive silicon characterization, enable first silicon bring-up, and build validation infrastructure while collaborating across Architecture, RTL, Firmware, Systems, and Customer Engineering. Strong leadership and a strategic validation mindset are required.
#J-18808-LjbffrLead Post-Silicon DVT Engineer for High-Speed ASICs in irvine at Unknown Company
This position is listed as full time and onsite.