Lead Physical Design Engineer - STA

We are looking for a Lead Static Timing Analysis Engineer to join our growing hardware engineering team.

You’ll lead timing convergence and methodology for our next-generation, ultra-low-power general-purpose processor, working across RTL, DFT, IP, physical design, and post-silicon teams.

This is an opportunity to join a newly formed organization early and help shape products from initial design through tape-out and volume production.

Key Responsibilities

• Develop STA flows and methodology using Cadence Tempus or Synopsys PrimeTime for advanced FinFET technologies.
• Own timing convergence for IP, subsystem, and SoC blocks.
• Define timing corners, margins, extraction methodology, and signoff correlation.
• Develop slew, glitch/noise, and custom timing checks.
• Define and drive SDC constraints with RTL, DFT, and IP teams.

Required Qualifications

• M.S. in Electrical Engineering with 5+ years of industry experience, or Ph.D. with 3+ years.
• Multiple STA signoffs/tape-outs at 12nm or below.
• Strong experience with Cadence, Synopsys, or Mentor EDA tools.
• Hands-on experience with high-frequency, low-power timing convergence.
• Deep knowledge of STA, constraints, exceptions, corners, voltage definitions, and timing margins.
• Strong TCL, shell, and Python scripting skills.
• Understanding of low-power implementation and power/timing tradeoffs.

Preferred

• Knowledge of computer architecture, physical design, ASIC implementation, and full-chip signoff.
• Experience with deep-submicron/SOI technologies and CAD/PD flow development.
• Experience integrating analog or mixed-signal macros.

This role can be in San Francisco or Austin