TSMC Technology Inc. is seeking a highly experienced Physical Design Verification Lead to drive end-to-end verification for CPU blocks on advanced N2/N7 nodes at a customer site in the South Bay area.
You will lead the verification flow, address timing, power, and parasitic challenges, and mentor junior engineers. You will collaborate with STA teams for ECOs, optimize CTS and Place & Route, and ensure successful production tapeouts with robust DRC/LVS/ERC checks.
#J-18808-LjbffrLead PD Verification for CPU Blocks & Tapeouts in california at Unknown Company
This position is listed as full time and onsite.