TylSemi, Inc. in San Jose, CA seeks a Principal Mixed-Signal RTL Design Engineer to lead micro-architecture and RTL for chiplet power optimization for AI/HPC. You will own digital control loops, design DPWM modulators, and collaborate with analog teams to ensure robust silicon performance.
Ideal candidates have 8+ years in power management ICs or high-performance mixed-signal design, with strong RTL coding skills and a track record of delivering production-quality blocks.
#J-18808-LjbffrLead Mixed-Signal RTL Designer for AI Power ICs in san jose at Unknown Company
This position is listed as full time and onsite.