Stellent IT LLC in San Jose, CA, seeks a Principal Design Engineer to lead RTL development for the Memory Controller, with deep expertise in ARM CHI-G and DFI interfaces. This onsite role will extend an existing controller to meet new architectural requirements and performance targets.
You will own microarchitecture updates, implement CHI-G/DFI logic, and collaborate with verification, DFT, and physical design teams to meet PPA goals. 8+ years of RTL experience in DDR subsystems are required.
#J-18808-LjbffrLead Memory Controller RTL Engineer (CHI-G/DFI) in san jose at Unknown Company
This position is listed as full time and onsite.