Lead IC Design Engineer: STA, Synthesis & Timing Closure

Broadcom, Inc. in San Jose, CA seeks a lead STA/Synthesis engineer to drive timing closure for complex IP and ASIC blocks in advanced nodes.

You will develop timing constraints, run static timing analysis with PrimeTime/Tempus, perform synthesis and timing audits, and automate analysis with Tcl or Perl; provide clock tree guidance.

Requires 12+ years in high‑complexity silicon, RTL/P&R experience, and strong collaboration skills.