Celero Communications is seeking a Senior/Principal Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks in our advanced optical communication systems. You will lead layout development of ADCs, DACs, PLLs, and other high-performance circuits, interfacing with circuit designers, CAD/PDK teams, and fellow layout engineers to ensure first-pass silicon success.
You will mentor junior engineers across time zones and contribute to chip-level planning,
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This position is listed as full time and onsite.