Lead, HBM Memory Subsystem Validation

AMD in Santa Clara, CA is seeking a Memory Sub-system Validation Lead to drive pre- and post-silicon validation of on-die HBM for the Datacenter GPU line. You will partner with DRAM, Memory Controller, DV, DDR PHY, DRAM product engineering and software teams to ensure memory designs meet quality standards.

As a hands-on leader, you will mentor engineers, develop test plans, and lead by example in a lab environment, delivering thorough validation results and clear defects to mass production.