Celero Communications, Inc. is seeking a Principal Physical Verification Engineer in San Jose, CA. You will lead the full-chip PV effort, own execution plans, and drive milestones toward tapeout readiness.
Collaborate with analog and IP teams to ensure clean integration and use ICV/Calibre tools to validate DRC/ERC/LVS results. The role requires a Bachelor’s or Master’s in Electrical Engineering and 7+ years of full-chip PV experience, with Tcl/Python scripting and strong cross-functional
#J-18808-LjbffrLead Full-Chip PV Engineer: Tapeout Ready in san jose at Unknown Company
This position is listed as full time and onsite.