Celero Communications, Inc. in San Jose, CA, is seeking a Principal Physical Verification Engineer to own all aspects of full-chip PV on advanced process nodes. You will collaborate with Analog and Physical Design teams to ensure tapeout readiness and high-quality DRC/LVS results.
The role requires 7+ years of PV experience, expertise with ICV/Calibre, and scripting skills in Tcl/Python. The position offers competitive base salary, strong growth, and exposure to cutting-edge 7nm/5nm tech.
#J-18808-LjbffrLead Full-Chip PV Engineer in san jose at Unknown Company
This position is listed as full time and onsite.