Celero Communications, Inc. is seeking a Full-Chip Physical Verification Engineer to own all aspects of PV execution on advanced nodes.
You will lead full-chip and block PV checks, drive schedules, and ensure tapeout readiness while collaborating with Analog and Physical Design teams to meet performance and manufacturability targets. The role requires a 7+ year track record in full-chip PV, experience with ICV/Calibre, and scripting skills in Python/Tcl.
#J-18808-LjbffrLead Full-Chip Physical Verification Engineer in san jose at Unknown Company
This position is listed as full time and onsite.