Lead FPGA Design Engineer - AI-Driven Hardware

Palo Alto Networks, Inc. is seeking an experienced FPGA/ASIC engineer to own the design from architecture through RTL and timing closure. You will work with cross-functional teams to deliver high-performance FPGA platforms for next‑generation firewalls.

The role emphasizes SystemVerilog/Verilog RTL, Synthesis with Vivado/Quartus/Synopsys, and lab bring-up on FPGA platforms. Collaboration and leadership are essential for success.