Lead FPGA & ASIC Design Manager, Compute Test

Teradyne in North Reading, MA, seeks an ASIC and Logic Design Engineering Manager to lead a 4–6 person FPGA/ASIC team for Compute Test products. You will oversee 2–3 FPGA/digital IP projects, collaborate across disciplines, and ensure timely deliverables in budget.

The role requires RTL coding, strong leadership, and experience with Vivado/Quartus, Cadence, clocking constraints, and high‑volume hardware development. Excellent communication skills are essential.