Cspeed IO in Palo Alto seeks an experienced FEA engineer to drive thermal and structural analysis for optical engine packages. You will build and validate models that influence architecture decisions and qualification, with close collaboration across design, packaging, and suppliers.
The role requires a PhD or MS in engineering, 6+ years of semiconductor packaging FEA, and proficiency in one major FEA/CFD tool plus a second for the complementary domain; experience with 2.5D/3D integration and
#J-18808-LjbffrLead FEA Packaging Engineer – Optical ICs in palo alto at Unknown Company
This position is listed as full time and onsite.