Lead DRAM RTL Design Engineer - PPA Mastery

Micron Technology is seeking a Principal RTL Design Engineer to lead the RTL design lifecycle for DRAM IP, from architecture through signoff, at our Boise, Idaho site. You will drive high-performance, power- and area-efficient RTL solutions and partner with physical design, verification, and architecture teams to meet tight PPA targets.

The role requires strong Verilog/SystemVerilog skills, ASIC low-power experience (UPF), and a track record of pre-silicon RTL/IP ownership.