Lead Digital Verification Engineer – Space/ASIC (LEO)

E-Space is looking for a Digital Design Verification Engineer to join their team in Saratoga, California. The ideal candidate will verify custom ASICs for satellite and wireless telephony, leveraging over 10 years of design verification experience in the semiconductor industry. Expertise in Verilog, SystemVerilog, and UVM is essential. This full-time position offers a target base pay of $120,000 – $220,000 annually, with significant opportunities to innovate in satellite technology. Come make a difference at E-Space.
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