Lead Digital ASIC Design Engineer (Onsite Cambridge)

Draper Laboratory in Cambridge, MA, seeks a Senior Digital ASIC Designer to implement high-performance digital ICs from RTL through synthesis.

Responsibilities include system-level design, optimization for performance and power, and leadership of multidisciplinary teams. Requires 7–10 years (or 5–10 with a Master’s) in ASIC hardware, with Cadence/Synopsys flows and SystemVerilog, Verilog or VHDL proficiency. On-site in Cambridge; US security clearance required.