Lead Digital ASIC Architect for Scientific Instrumentation

Brookhaven National Laboratory seeks a Senior Digital ASIC Design Engineer to lead architecture, RTL design, and integration of digital ASICs for detector readout and related instrumentation.

You will collaborate with a multidisciplinary team, develop synthesizable RTL in SystemVerilog/Verilog, and work with Cadence and Synopsys environments to ensure successful tapeout and integration at Brookhaven Lab in Upton, NY.