Lead Design Verification Architect – Cache-Coherent Interconnect

SiFive, a leader in RISC-V-based compute, seeks a Principal Design Verification Engineer to steer verification for a cache-coherent interconnect subsystem used in high-performance CPU/SoC platforms.

You will partner with architecture, RTL, formal, and performance teams to ensure protocol correctness, ordering, flow control, and robust integration across interfaces while mentoring engineers and advancing reusable DV infrastructure.