Lead Design Verification Architect — Cache Coherence

SiFive is seeking a Principal Design Verification Engineer to lead verification strategy and execution for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms. This prime role requires defining architecture-aware verification plans, identifying risks early, and elevating verification quality across architecture, RTL, formal, and performance teams.

You will drive verification across interfaces, bridges, and data-movement paths, develop