Lead Design Engineer — RTL, Timing & Tapeout

Cadence Design Systems in Cary, NC seeks an experienced IC design engineer to lead timing closure and tape-out activities for Palladium and Protium SOCs. You will contribute to RTL synthesis, floorplanning, clock-tree construction, and physical verification, collaborating with Front End RTL and Back End Verification teams.

The role requires 5+ years of E/E experience or 3+ years with MS, proficiency with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus), and familiarity with 5nm/3nm/2nm