Cadence Design Systems seeks a Director of Design Verification to lead the Processor Verification team, overseeing verification of microprocessor cores and peripherals in a high-impact setting. The role requires deep DV expertise and strong leadership to guide 7–10 engineers.
Location includes San Jose, CA and Austin, TX, with a competitive salary and incentives. The ideal candidate will have 17+ years of verification experience, a BS in EE/CE, and mastery of SystemVerilog/UVM, assembly
#J-18808-LjbffrLead CPU Verification Architect — Equity Eligible in san jose at Unknown Company
This position is listed as full time and onsite.