Lead ASIC Verification Engineer - UVM/SystemVerilog

Mirafra Technologies is seeking an experienced verification Engineer to architect block and full-chip verification environments using HVLs and constrained random methods for SOCs with embedded CPUs and mixed-signal interfaces. The role requires UVM, SystemVerilog, and SVA expertise to drive test plans, coverage metrics, and bug replication in simulation.

Responsibilities include debugging RTL/gate simulations with design teams, writing diagnostics for FPGA prototype validation and ASIC, and