Asteralabs in California is looking for a Principal Design Verification Engineer to lead the functional verification of advanced ASICs and develop robust verification methodologies. Candidates should possess 8+ years of experience in SoC verification and be proficient in SystemVerilog/UVM, C/C++, and Python.
The role involves comprehensive verification processes, working closely with RTL designers and validation teams. Competitive salary range from $185,000 to $230,000, plus potential bonuses and benefits offered.
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