Celero Communications seeks a Senior/Principal Analog Layout Engineer in Irvine, CA to drive layout development for analog/mixed-signal IP blocks such as ADCs, DACs, and PLLs within a fast-paced AMS design team.
You will interface with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success while mentoring others and contributing to chip development.
#J-18808-LjbffrLead Analog Layout Architect for High-Speed IP in irvine at Unknown Company
This position is listed as full time and onsite.