Cadence Design Systems in California seeks a Principal Analog IC Designer to drive analog/mixed-signal circuit blocks from concept to verification. You will apply CAD tools for simulation, layout, and physical verification while leveraging Cadence tools and lab testing to achieve performance above 10Gbps in advanced <28nm processes.
The role requires a minimum of 7 years in CMOS SerDes or high-speed I/O design, with a strong background in jitter and signal integrity.
#J-18808-LjbffrLead Analog IC Designer - High-Speed SerDes in san jose at Unknown Company
This position is listed as full time and onsite.