IP / SoC Design Verification Engineer

Job Title: IP / SoC Design Verification Engineer

Location: Dallas, TX (On-site)

Employment Type: Contract

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Electronics, or a related field

Job Description

We are seeking a motivated and detail-oriented IP / SoC Design Verification Engineer to join our engineering team in Dallas, TX. The candidate will be responsible for verifying complex IP and System-on-Chip (SoC) designs using functional and formal verification methodologies.

The ideal candidate will have a strong foundation in RTL design, SystemVerilog, UVM, digital design, and computer architecture. This role involves developing verification environments, executing simulation-based tests, debugging RTL issues, and collaborating with design and architecture teams to ensure the functionality, reliability, and quality of semiconductor IP and SoC designs.

Key Responsibilities

Develop and execute verification plans for IP-level and SoC designs based on functional specifications.

Design, implement, and maintain scalable testbenches using SystemVerilog and UVM methodology.

Perform functional and formal verification of RTL designs to ensure specification compliance.

Develop directed and constrained-random test cases to validate functional scenarios and corner cases.

Execute simulation, regression, and coverage-driven verification activities.

Debug simulation failures, analyze waveforms, and identify root causes of design issues.

Develop and maintain assertions, functional coverage models, and code coverage metrics.

Create reusable verification components, environments, and Verification IP (VIP).

Perform IP-level and SoC integration verification for protocols such as AXI, AHB, APB, and PCIe.

Collaborate with RTL designers, architects, and integration teams to resolve bugs and improve design quality.

Utilize EDA tools from Synopsys, Cadence, and Siemens for simulation, verification, and debugging.

Develop scripts using Python, Perl, or Shell to automate verification workflows.

Review RTL implementations and verification results to ensure design readiness and quality.

Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Electronics, or a related discipline.

Strong understanding of digital logic design, RTL design, and computer architecture fundamentals.

Knowledge of functional verification and formal verification concepts.

Hands-on experience or academic project exposure to SystemVerilog and UVM.

Familiarity with testbench development, simulation, and regression testing.

Understanding of constrained-random verification, assertions, and functional coverage.

Knowledge of IP design, SoC architecture, and standard protocols such as AXI, AHB, APB, or PCIe.

Familiarity with RTL debugging, waveform analysis, and EDA verification tools.

Basic scripting knowledge in Python, Perl, or Shell.

Strong analytical, problem-solving, communication, and teamwork skills.

Preferred Qualifications

Experience or academic project exposure in IP-level or SoC design verification.

Familiarity with formal verification tools and methodologies.

Knowledge of semiconductor design and verification workflows.

Exposure to Synopsys, Cadence, or Siemens EDA tool suites.

Relevant coursework, internships, or certifications in IP Design or SoC Verification.