Directed/constrained random test generation in UVM
Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
Run RTL and gate level functional verification, debug failures, and analyze coverage
Support mixed‑signal verification using Verilog models of analog IP
Requirements
Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
IP or SoC verification experience using System Verilog/UVM
Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
Implementation of verification environments that include use of constrained-random stimulus