Etched is seeking a Design Verification Engineer for the Interface IP DV team. You will validate the architecture requirements across IP subsystems and interfaces, ensuring correctness and performance from hardware to software.
The role demands creativity and deep technical ability to tackle challenging verification tasks. You will own end-to-end verification for IP subsystems, work with vendor IP configurations, and develop scalable testbenches using SystemVerilog/UVM.
#J-18808-LjbffrInterface IP Design Verification Engineer (PCIe/Ethernet) in san jose at Unknown Company
This position is listed as full time and onsite.