Teradyne in North Reading, MA seeks an ASIC/FPGA Methodology Engineer to define, develop, and maintain FPGA/ASIC design and verification workflows. You will collaborate with design teams, enable RTL development with Verilog, and optimize flows for Vivado/Quartus in a Linux environment.
The role requires 3+ years in FPGA/embedded design, strong design principles, and experience with CI/CD and related tooling.
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