Annapurna Labs (U.S.) Inc. is seeking an ASIC Design Engineer in Cupertino, CA to design and optimize high-performance RTL for AWS data-center SoCs including Inferentia. You will contribute to microarchitectures, SystemVerilog RTL, and post-silicon validation with a team of architects and verification engineers.
Ideal candidates have a strong background in RTL design, power/area trade-offs, and a passion for innovation, accelerated by AWS culture and collaboration across multiple disciplines.
#J-18808-LjbffrInnovative ASIC Design Engineer II | RTL & Microarchitecture in cupertino at Unknown Company
This position is listed as full time and onsite.