IC Package Design Engineer - Multi-Die Chiplet Packaging

Piper Companies seeks an IC Package Design Engineer to lead the physical layout of advanced multi-die substrates that integrate chiplets into a high-density, high-performance package. This onsite role is based near San Jose, CA.

You will collaborate with ASIC, signal integrity, and mechanical teams, own the full layout process, and use Siemens Xpedition and Cadence Allegro APD to deliver manufacturable designs. An 8+ year background and US security-clearance readiness are preferred.