Piper Companies is seeking an IC Package Design Engineer to lead the physical layout of multi-die substrates for a high-density, chiplet-based package. This onsite role is based near San Jose, CA.
You will own the full layout process, collaborate with ASIC, signal integrity, power, and mechanical teams, and drive routing feasibility using Siemens Xpedition and Cadence Allegro APD to ensure manufacturability and performance.
#J-18808-LjbffrIC Package Design Engineer: Multi-Die Chiplet Packaging in san jose at Unknown Company
This position is listed as full time and onsite.