Hybrid ASIC Timing & SDC Engineer

CAONE in San Jose, CA is seeking an experienced ASIC Design Hardware Engineer focused on SDC/STA. You will develop timing constraints, work with front-end/back-end teams, and validate constraints with industry tools to enable physical design closure.

Candidates should have a degree in Electrical or Computer Engineering and 6+ years of ASIC experience (or a Master’s with 3+ years). Proficiency in Verilog/SystemVerilog, TCL, and Primetime is required, with strong scripting and problem-solving