High-Speed ASIC Design Engineer RTL & Timing

Lumicity, located on-site in San Jose, CA, is offering an exciting opportunity to work on high-speed digital integrated circuits. The successful candidate will engage in High-Speed Digital Design, RTL Design, and Synthesis for next-generation products. Required qualifications include a B.S. or M.S. in Electrical Engineering and extensive experience with Verilog or SystemVerilog, as well as EDA tools like Cadence and Synopsys. Ideal candidates will have a strong foundation in Digital ASIC Design and scripting experience with Python, TCL, or Perl.
#J-18808-Ljbffr