Hardware Design Verification Engineer
We are seeking an experienced Hardware Design Verification Engineer to support the verification of accelerated networking IP and hardware solutions. The ideal candidate will have strong expertise in SystemVerilog, UVM, and hardware verification methodologies, with experience validating complex IP and SoC-level designs in a pre-silicon environment.
Responsibilities include developing, executing, and maintaining verification test plans for hardware IP and SoC-level designs; building, debugging, and enhancing verification environments using SystemVerilog and UVM; validating hardware features through comprehensive test coverage and scenario execution; analyzing and debugging design issues, working closely with design and architecture teams to identify root causes and implement solutions; developing and maintaining automation scripts using Python, Perl, or similar languages; monitoring verification results and recommending modifications to ensure designs meet functional and performance specifications; supporting the development, testing, and validation of hardware prototypes and simulation models; and evaluating hardware configurations based on technical requirements, performance expectations, security considerations, and project constraints.
MUST HAVES:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related engineering discipline.
- 10+ years of hardware design verification experience.
- Strong hands-on experience with SystemVerilog, UVM (Universal Verification Methodology), Python and/or Perl scripting.
- Experience with IP-level and/or SoC-level pre-silicon verification.
- Strong understanding of RTL design and verification methodologies.
- Experience developing and executing test plans, debugging issues, and validating functional scenarios.
- Excellent analytical, problem-solving, verbal, and written communication skills.
- Ability to work independently and collaborate effectively in cross-functional teams.
NICE TO HAVES:
- Verification experience involving networking datapaths, storage datapaths, SmartNICs, accelerated networking technologies.
- Knowledge of industry-standard protocols, including Ethernet, AXI, AHB, PCIe.
- Experience verifying complex hardware systems.
- Master's degree with relevant industry experience.
- Prior Microsoft experience with at least one continuous year of service.
The strongest candidates will demonstrate deep hands-on expertise in SystemVerilog, UVM, and scripting; proven success verifying IP and SoC-level designs; experience with networking technologies and protocols; strong debugging and root-cause analysis skills; ability to contribute quickly within an established verification environment; and effective collaboration with hardware design and architecture teams.
Job Type & Location: This is a contract position based out of Redmond, WA.
Pay and Benefits: The pay range for this position is $80.00 - $90.00/hr. Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include medical, dental & vision, critical illness, accident, and hospital insurance, 401(k) retirement plan, life insurance, short and long-term disability, health spending account, transportation benefits, employee assistance program, and time off/leave (PTO, vacation or sick leave).
Workplace Type: This is a fully remote position.
Application Deadline: This position is anticipated to close on Aug 17, 2026.
About Actalent: Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation, and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia, and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information, or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email for other accommodation options.
San Francisco Fair Chance Ordinance: For all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.
Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.
Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.